In 2019, AMD began using a 7 nm node for the core complex die (CCD) of the Zen 2 microarchitecture and a 12 nm node for the IO die. In a recent interview with Tom’s Hardware, AMD stated that Zen 4 would feature three node bumps, from 5 nm for the CCD to 6 nm for the IO die to 7 nm for the V-Cache.
AMD recently spoke at the ISSCC and discussed some difficulties when stacking one node over another. The V-Caches on the 7950X3D and the original 5800X3D are placed over their respective L3 caches to enable the connection. The configuration also shields the V-Cache from the heat generated by the cores. The V-Cache in the 7950X3D, on the other hand, overlaps with the L2 caches on the borders of the cores, whereas it neatly fits over the L3 cache in the 5800X3D.
AMD raised the amount of L2 cache in each core from 0.5 MB in Zen 3 to 1 MB in Zen 4, contributing to some of the issues. The through-silicon vias (TSVs) that supply power to the V-Cache was poked through the L2 caches to get past the additional space restrictions. The signal TSVs still originate from the controller in the CCD’s center, but AMD also made adjustments to them, cutting their footprint in half.
AMD kept the same 4.7 B transistors while reducing the V-Cache from 41 mm2 to 36 mm2. The cache is produced by TSMC using a new iteration of the 7 nm node it created specifically for SRAM. Even though the CCD was produced on the considerably smaller 5 nm node, the V-Cache has 32% more transistors per square millimeter than the CCD.
With all of the improvements and workarounds AMD implemented, bandwidth increased by 25% to 2.5 TB/s, and efficiency increased by an undetermined amount. A supplemental chiplet is effective for nine months between the first and second generations. It will be worthwhile when the Ryzen 7 7800X3D is released in a month.
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